This invention is in the field of solid-state integrated circuits, and is more specifically directed to the layout and arrangement of device arrays and peripheral circuitry in such integrated circuits.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Modern solid-state memory is realized by various memory technologies. Static random access memory (SRAM) has become the memory technology of choice in many modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory. Typically, each SRAM cell is constructed as a cross-coupled pair of inverters. Another solid-state memory type is referred to as dynamic RAM (DRAM), which realizes each memory cell as a single capacitor in combination with a single pass transistor for selectively coupling one of the capacitor plates to a bit line, for read and write access. DRAM technology attains higher memory density (bits per unit area), but requires periodic refreshing (read followed by write back) to retain the stored data state. Various types of non-volatile memory, including mask-programmable read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), ferroelectric RAM (FeRAM, or FRAM), and the like are well-known in the art.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes, such as metal-oxide-semiconductor (MOS) transistor gates, into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits.
Electrical effects dependent on the proximity and structure of neighboring devices have been observed in transistors constructed with deep sub-micron feature sizes (e.g., gate widths of 90 nm and below). Various causes and manifestations of these “proximity” effects have been characterized. These various proximity effects have been observed to impart significant variations in drain-to-source current of MOS transistors.
One type of proximity effect is known in the art as the “well proximity effect”, as described in Drennan et al., “Implications of Proximity Effects for Analog Design”, Paper 8.6, Custom Integrated Circuits Conference (IEEE, 2006). As described in that paper, this effect is caused by the scattering of dopant atoms from edges of the photoresist mask used to form doped wells in MOS integrated circuits. Because of this scattering, the channel regions of transistors nearer to the edge of the well are doped to a higher surface concentration than for those transistors farther away from the well edge. This effect appears as variations in threshold voltage and other electrical characteristics.
Other proximity effects include those due to lithographic proximity in the polysilicon gate level, in which the photolithographic patterning of a polysilicon gate structure is affected by other nearby gate structures. Regularity in gate spacing and width is known to reduce variation due to lithographic proximity effects. Lithographic proximity effects have also been observed at the contact level. In addition, nearby contact openings in overlying insulator films have been observed to affect strain effects in MOS transistors, depending on the stresses (i.e., compressive or tensile properties) in that overlying film.
By way of further background, recent advances in semiconductor technology as applied to integrated circuits include the use of “strain engineering” (or, alternatively, “stress engineering”) in the manufacture of semiconductor device structures. It has been discovered that the tuning of strain in the crystal lattice of MOS transistor channel regions can enhance carrier mobility in those regions. As is fundamental in MOS device technology, the source/drain current (i.e., drive) of an MOS transistor in both the triode and saturation regions is proportional to carrier mobility in the channel region. In a general sense, compressive stress enhances hole mobility in the channel region of a p-channel MOS transistor, and tensile stress enhances electron mobility in the channel region of an n-channel MOS transistor. Typically, p-channel MOS transistors exhibit lower drive capability than n-channel MOS transistors in typical modern integrated circuits. As such, strain engineering techniques are more typically applied to p-channel MOS transistors than to n-channel MOS transistors, in current day manufacturing technology.
Various strain engineering approaches are known in the art. One approach is known as “embedded SiGe” (or “eSiGe”), in which the source and drain regions of a p-channel MOS transistor structure are etched from the silicon substrate or well region, and are replaced with a silicon-germanium alloy formed by selective epitaxy. Because of the germanium atoms within the silicon crystal lattice, the germanium constituting as much as 30% (atomic) of the alloy, eSiGe exhibits a larger lattice constant than does silicon (i.e., the distance between unit cells in the crystal lattice for SiGe is greater than in single-crystal silicon). Embedded eSiGe source/drain regions thus apply compressive stress to the channel region of the p-channel MOS transistor being formed. This compressive stress in the channel increases the hole mobility of the p-channel MOS transistor, and enhances its performance. Another conventional strain engineering approach known as “dual stress liner”, or “DSL”, technology involves the formation of a silicon nitride layer of either tensile or compressive characteristics over the active regions (i.e., source and drain regions) of transistors that are to receive the resulting stress. Tensile silicon nitride is used to enhance n-channel MOS transistors, and compressive silicon nitride is used to enhance p-channel MOS transistors. These strain engineering approaches have become important as device scaling has reached the very deep submicron regime (e.g., gate widths below 50 nm).
But at those small feature sizes, transistors become more sensitive to proximity effects. In addition, the effects of these strain engineering techniques often extend to neighboring devices and structures. Indeed, the performance enhancement mechanism of eSiGe technology essentially operates at a distance and can itself be considered as a “proximity effect”, considering that the eSiGe source and drain regions impart a strain to the adjacent channel region, which is not formed of the alloy. Variations in the strain imparted to transistor channel regions resulting from variations in the layout of strain-producing structures thus must be considered.
One source of proximity effects caused by variations in mechanical strain imparted to MOS transistor channel regions is referred to in the above-cited Drennan et al. paper as the Shallow Trench Isolation stress effect. Strain variation due to this effect results from stresses within the shallow trench isolation structures that define active regions (e.g., source and drain regions) of MOS transistors. As known in the art, relatively thick isolation dielectric (e.g., silicon dioxide) structures at selected surface locations of the integrated circuit define semiconductor active regions into which MOS transistors and other semiconductor circuit elements are formed. In modern integrated circuits, particularly those in the sub-micron regime, this isolation dielectric is formed by a masked recess etch into the surface of the substrate (or silicon layer in a silicon-on-insulator environment), followed by deposition of a dielectric film such as silicon dioxide into those recesses. The deposited silicon dioxide in these “shallow trench isolation” structures can exhibit compressive or tensile properties, which can impart strain to the neighboring active regions including MOS transistor channel regions. The extent of this imparted strain has been observed to depend on the proximity of the transistor to the shallow trench isolation structure, as well as the volume of the isolation dielectric itself (i.e., the proximity and size of a neighboring active region on the other side of the isolation structure).
As known in the art, memory arrays involve a relatively large area of similar structures (i.e., the memory cells), and as such are conducive to being constructed in very regular fashion. This regularity in construction will, theoretically, reduce variation in array transistor performance due to proximity effects. However, those memory cells that are at the edges of a memory array are necessarily in a different structural environment than those in the center of the array. As such, variation in transistor performance between edge cells and cells interior to the array is often evident. In many memory designs, yield analysis has shown preponderance for data storage failures (failed read or failed write) for memory cells at array edges, as compared with interior cells.
A conventional approach for addressing this device variation between array edge cells and array interior cells is to construct “dummy” memory cells around the edges of the memory array. These dummy cells are constructed similarly as the memory cells themselves, but without electrical connection. Of course, the chip area required for these memory cells adds to the manufacturing cost of the integrated circuit containing the memory.
Other types of integrated circuit functions that are also constructed as an array or region of repetitive device structures, similarly suffer from device variations due to proximity effect. For example, many modern logic circuits are constructed as a “sea of gates” or another type of repetitive construction at lower levels in the integrated circuit structure. These logic circuits can be readily customized to realize a particular logic function at upper structural levels, such as in the routing of metal conductors to the transistors and gates. Proximity effects similarly result in transistor performance variation between transistors and gates at the edges of the repetitive structures, and those in the interior of the logic array.